---------------------------------------------------------------------------
-- Company     : Vim Inc
-- Author(s)   : Fabien Marteau
-- 
-- Creation Date : 24/04/2008
-- File          : Top.vhd
--
-- Abstract : Blink blink a led ... 
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

---------------------------------------------------------------------------
Entity Top is 
---------------------------------------------------------------------------
port 
(
			-- Atmega128 port
			Address_H     : in std_logic_vector( 7 downto 0);
			DA            : inout std_logic_vector( 7 downto 0);
			ALE           : in std_logic ;
			RD            : in std_logic ;
			WR            : in std_logic ;
			DIR_buffer    : out std_logic ;
			
			-- Clock and reset
			clk           : in std_logic ;
			reset_n       : in std_logic ;

			-- Output
			LED           : out std_logic ;
			pwm 					: out std_logic ;
			pwm_dir       : out std_logic 

);
end entity;


---------------------------------------------------------------------------
Architecture Top_1 of Top is
---------------------------------------------------------------------------

	component	 atmega_wrapper
		port (
			-- Atmega128 port
			Address_H     : in std_logic_vector( 7 downto 0);
			DA            : inout std_logic_vector( 7 downto 0);
			ALE           : in std_logic ;
			RD            : in std_logic ;
			WR            : in std_logic ;
			DIR_buffer    : out std_logic ;

			-- Wishbone port
			wbm_address   : out std_logic_vector( 15 downto 0);
			wbm_readdata  : in std_logic_vector( 7 downto 0);
			wbm_writedata : out std_logic_vector( 7 downto 0);
			wbm_strobe    : out std_logic ;
			wbm_write     : out std_logic ;
			wbm_ack       : in std_logic ;
			wbm_cycle     : out std_logic ;

			-- clock 50MHz and reset
			clk           : in std_logic ;
			reset_n       : in std_logic 

			);
	end component;

	component Wb_led
		port (
			-- Syscon signals
			reset_n       : in std_logic ;
			clk           : in std_logic ;
			-- Wishbone signals
			wbs_writedata : in std_logic_vector( 7 downto 0);
			wbs_readdata  : out std_logic_vector( 7 downto 0);
			wbs_strobe    : in std_logic ;
			wbs_write     : in std_logic ;
			wbs_ack       : out std_logic;
			-- out signals
			LED           : out std_logic 
			);
	end component;
	
	component Wb_pwm
		port (
			-- syscon signals
			reset_n       : in std_logic ;
			clk           : in std_logic ;
			--Wishbone signals
			wbs_address   : in std_logic ;
			wbs_writedata : in std_logic_vector( 7 downto 0);
			wbs_readdata  : out std_logic_vector( 7 downto 0);
			wbs_strobe    : in std_logic ;
			wbs_write     : in std_logic ;
			wbs_ack       : out std_logic ;
			-- output
			pwm           : out std_logic ;
			pwm_dir       : out std_logic 

			);
	end component;

	component intercon
		port (
			-- general clock and reset
			gls_reset_n       : in std_logic ;
			gls_clock         : in std_logic ;

			-- Master wrapper port
			wbm_reset_n       : out std_logic ;
			wbm_clk           : out std_logic ;

			wbm_address       : in std_logic_vector( 15 downto 0);
			wbm_readdata      : out std_logic_vector( 7 downto 0);
			wbm_writedata     : in std_logic_vector( 7 downto 0);
			wbm_strobe        : in std_logic ;
			wbm_write         : in std_logic ;
			wbm_ack           : out std_logic ;
			wbm_cycle         : in std_logic ;

			-- Slave LED port
			wbs_reset_n       : out std_logic ;
			wbs_clk           : out std_logic ;

			wbs_writedata     : out std_logic_vector(7  downto 0);
			wbs_readdata      : in std_logic_vector( 7 downto 0);
			wbs_strobe        : out std_logic ;
			wbs_write         : out std_logic ;
			wbs_ack           : in std_logic;

			-- Slave pwm port
			wbs_reset_n_pwm   : out std_logic ;
			wbs_clk_pwm       : out std_logic ;

			wbs_address_pwm   : out std_logic;
			wbs_writedata_pwm : out std_logic_vector( 7 downto 0);
			wbs_readdata_pwm  : in  std_logic_vector( 7 downto 0);
			wbs_strobe_pwm    : out std_logic ;
			wbs_write_pwm     : out  std_logic ;
			wbs_ack_pwm       : in  std_logic 

			);
	end component;

	-- Master wrapper port
	signal		wbm_reset_n  : std_logic ;
	signal		wbm_clk      : std_logic ;

	signal		wbm_address  : std_logic_vector( 15 downto 0);
	signal		wbm_readdata : std_logic_vector( 7 downto 0);
	signal		wbm_writedata: std_logic_vector( 7 downto 0);
	signal		wbm_strobe   : std_logic ;
	signal		wbm_write    : std_logic ;
	signal		wbm_ack      : std_logic ;
	signal		wbm_cycle    : std_logic ;

	-- Slave LED port
	signal		wbs_reset_n  : std_logic ;
	signal		wbs_clk      : std_logic ;

	signal		wbs_writedata  : std_logic_vector( 7 downto 0);
	signal		wbs_readdata   : std_logic_vector( 7 downto 0);
	signal		wbs_strobe     : std_logic ;
	signal		wbs_write      : std_logic ;
	signal		wbs_ack        : std_logic ;

	-- Slave pwm port
	signal		wbs_reset_n_pwm   : std_logic ;
	signal		wbs_clk_pwm       : std_logic ;

	signal    wbs_address_pwm     : std_logic ;
	signal		wbs_writedata_pwm   : std_logic_vector( 7 downto 0);
	signal		wbs_readdata_pwm    : std_logic_vector( 7 downto 0);
	signal		wbs_strobe_pwm      : std_logic ;
	signal		wbs_write_pwm       : std_logic ;
	signal		wbs_ack_pwm         : std_logic ;


begin

	connect_intercon : intercon
	port map (
		-- general clock and reset
		gls_reset_n   => reset_n,
		gls_clock     => clk,

		-- Master wrapper port
		wbm_reset_n   => wbm_reset_n,
		wbm_clk       => wbm_clk      ,
                                  
		wbm_address   => wbm_address  ,
		wbm_readdata  => wbm_readdata ,
		wbm_writedata => wbm_writedata,
		wbm_strobe    => wbm_strobe   ,
		wbm_write     => wbm_write    ,
		wbm_ack       => wbm_ack      ,
		wbm_cycle     => wbm_cycle    ,
                                  
		-- Slave LED port
		wbs_reset_n   => wbs_reset_n  ,
		wbs_clk       => wbs_clk      ,
                                  
		wbs_writedata => wbs_writedata,
		wbs_readdata  => wbs_readdata ,
		wbs_strobe    => wbs_strobe   ,
		wbs_write     => wbs_write    ,
	  wbs_ack       => wbs_ack,

		-- Slave pwm port
		wbs_reset_n_pwm   => wbs_reset_n_pwm  ,
		wbs_clk_pwm       => wbs_clk_pwm      ,
                     
		wbs_address_pwm       => wbs_address_pwm,
		wbs_writedata_pwm => wbs_writedata_pwm,
		wbs_readdata_pwm  => wbs_readdata_pwm ,
		wbs_strobe_pwm    => wbs_strobe_pwm   ,
		wbs_write_pwm     => wbs_write_pwm    ,
	  wbs_ack_pwm       => wbs_ack_pwm
		);

	connect_Wb_led : Wb_led
	port map (
		-- Syscon signals
		reset_n       => wbs_reset_n      ,
		clk           => wbs_clk          ,
		-- Wishbone signa-- Wishbone sls
		wbs_writedata => wbs_writedata,
		wbs_readdata  => wbs_readdata ,
		wbs_strobe    => wbs_strobe   ,
		wbs_write     => wbs_write    ,
		wbs_ack       => wbs_ack      ,
		-- out signals   -- out signal
		LED           => LED          
		);

	connect_Wb_pwm : Wb_pwm
	port map (
		-- syscon signals
		reset_n       => wbs_reset_n_pwm,
		clk           => wbs_clk_pwm,
		--Wishbone signals
		wbs_address   => wbs_address_pwm,
		wbs_writedata => wbs_writedata_pwm,
		wbs_readdata  => wbs_readdata_pwm,
		wbs_strobe    => wbs_strobe_pwm,
		wbs_write     => wbs_write_pwm,
		wbs_ack       => wbs_ack_pwm,
		-- output
		pwm           => pwm,
		pwm_dir           => pwm_dir

		);

	connect_atmega_wrapper : atmega_wrapper
	port map (
		-- Atmega128 port
		Address_H     => Address_H  ,
		DA            => DA         ,
		ALE           => ALE        ,
		RD            => RD         ,
		WR            => WR         ,
		DIR_buffer    => DIR_buffer ,

		-- Wishbone port
		wbm_address   => wbm_address  ,
		wbm_readdata  => wbm_readdata ,
		wbm_writedata => wbm_writedata,
		wbm_strobe    => wbm_strobe   ,
		wbm_write     => wbm_write    ,
		wbm_ack       => wbm_ack      ,
		wbm_cycle     => wbm_cycle    ,

		-- clock 50MHz and reset
		clk           => wbm_clk,
		reset_n       => wbm_reset_n
		);

end architecture Top_1;

